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679 lines
12 KiB
JavaScript
679 lines
12 KiB
JavaScript
/*
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RISC-V Code Mirror Mode
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Based on the mode present in the Venus Simulator
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Author: kvakil
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Source: https://github.com/kvakil/venus
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Forked by Matthew Nielsen (github.com/matthewnielsen27)
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*/
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const CodeMirror = require('codemirror')
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CodeMirror.defineMode('riscv', function (/* config */) {
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function regexFromWords(words, ins) {
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return new RegExp('^(?:' + words.join('|') + ')$', ins)
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}
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// Instructions
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// Part 1) Base Integer Instructions
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// a) Loads
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// b) Stores
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// c) Shifts
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// d) Arithmetic
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// e) Logical
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// f) Compare
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// g) Branches
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// h) Jump & Link
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// i) Synch
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// j) System
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// k) Counters
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// Part 2) RV Priveleged Instructions
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// a) CSR Access
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// b) Change Level
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// c) Trap Redirect
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// Part 3) Optional Multiply-Divide Instruction Extension: RVM
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// a) Multiply
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// b) Divide
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// c) Remainder
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// Part 4) Pseudo Instructions
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// a) Standard
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// b) Non-Standard
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// Part 5) Optional Compressed (16-bit) Instruction Extension: RVC
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// a) Loads
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// b) Stores
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// c) Arithmetic
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// d) Shifts
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// e) Branches
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// f) Jump
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// g) Jump & Link
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// h) System
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// Part 6) Optional Atomic Instruction Extension: RVA
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// a) Load
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// b) Store
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// c) Swap
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// d) Add
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// e) Logical
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// f) Min\Max
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// Part 7) Optional Floating-Point Instruction Extension: RVF, RVD, & RVQ
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// a) Move
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// b) Convert
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// c) Load
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// d) Store
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// e) Arithmetic
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// f) Mui-Add
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// g) Sign Inject
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// h) Min/Max
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// i) Compare
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// j) Categorization
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// k) Configuration
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var instructions = regexFromWords(
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[
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// Part 1) Base Integer Instructions
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// a) Loads
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// I) RV32I
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'lb',
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'lh',
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'lw',
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'lbu',
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'lhu',
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// II) RV64I and RV128I
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'ld',
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'lq',
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'lwu',
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'ldu',
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// b) Stores
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// I) RV32I
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'sb',
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'sh',
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'sw',
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// II) RV64I and RV128I
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'sd',
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'sq',
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// c) Shifts
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// I) RV32I
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'sll',
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'slli',
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'srl',
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'srli',
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'sra',
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'srai',
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// II) RV64I and RV128I
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'sllw',
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'slliw',
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'srlw',
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'srliw',
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'sraw',
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'sraiw',
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'slld',
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'sllid',
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'srld',
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'srlid',
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'srad',
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'sraid',
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// d) Arithmetic
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// I) RV32I
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'add',
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'addi',
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'sub',
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'lui',
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'auipc',
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// II) RV64I and RV128I
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'addw',
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'addiw',
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'subw',
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'addd',
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'addid',
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'subd',
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// e) Logical
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'xor',
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'xori',
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'or',
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'ori',
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'and',
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'andi',
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// f) Compare
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'slt',
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'slti',
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'sltu',
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'sltiu',
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// g) Branches
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'beq',
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'bne',
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'blt',
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'bge',
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'bltu',
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'bgeu',
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// h) Jump & Link
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'jal',
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'jalr',
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// i) Synch
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'fence',
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'fence.i',
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// j) System
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'scall',
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'sbreak',
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// k) Counters
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'rdcycle',
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'rdcycleh',
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'rdtime',
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'rdtimeh',
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'rdinstret',
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'rdinstreth',
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// Part 2) RV Priveleged Instructions
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// a) CSR Access
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'csrrw',
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'csrrs',
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'csrrc',
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'csrrwi',
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'csrrsi',
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'csrrci',
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// b) Change Level
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'ecall',
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'ebreak',
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'eret',
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// c) Trap Redirect
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'mrts',
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'mrth',
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'hrts',
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// Part 3) Optional Multiply-Divide Instruction Extension: RVM
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// a) Multiply
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// I) RV32M
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'mul',
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'mulh',
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'mulhsu',
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// II) RV64M and RV128M
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'mulw',
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'muld',
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// b) Divide
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// I) RV32M
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'div',
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'divu',
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// II) RV64M and RV128M
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'divw',
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'divd',
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// c) Remainder
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// I) RV32M
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'rem',
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'remu',
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// II) RV64M and RV128M
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'remw',
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'remuw',
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'remd',
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'remud',
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// Part 4) Pseudo Instructions
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// a) Standard Pseudo Instructions
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'beqz',
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'bgez',
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'bgt',
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'bgtu',
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'bgtz',
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'ble',
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'bleu',
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'blez',
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'bltz',
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'bnez',
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'call',
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'j',
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'jr',
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'la',
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'li',
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'mv',
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'neg',
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'nop',
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'ret',
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'not',
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'ret',
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'seqz',
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'sgtz',
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'sltz',
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'snez',
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'tail',
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// b) Non-Standard Pseudo Instructions
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'seq',
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'sge',
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'sgeu',
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'sgt',
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'sgtu',
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'sle',
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'sleu',
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'sne',
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// Part 5) Optional Compressed (16-bit) Instruction Extension: RVC
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// a) Loads
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'c.lw',
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'c.lwsp',
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'c.ld',
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'c.ldsp',
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'c.lq',
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'c.lqsp',
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// b) Stores
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'c.sw',
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'c.swsp',
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'c.sd',
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'c.sdsp',
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'c.sq',
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'c.sqsp',
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// c) Arithmetic
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'c.add',
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'c.addw',
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'c.addi',
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'c.addiw',
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'c.addi16sp',
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'c.addi2spn',
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'c.li',
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'c.lui',
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'c.mv',
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'c.sub',
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// d) Shifts
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'c.slli',
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// e) Branches
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'c.beqz',
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'c.bnez',
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// f) Jump
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'c.j',
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'c.jr',
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// g) Jump & Link
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'c.jal',
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'c.jalr',
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// h) System
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'c.ebreak',
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// Part 6) Optional Atomic Instruction Extrnsion: RVA
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// a) Load
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// I) RV32A
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'lr.w',
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// II) RV64A and RV128A
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'lr.d',
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'lr.q',
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// b) Store
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// I) RV32A
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'sc.w',
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// II) RV64A and RV128A
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'sc.d',
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'sc.q',
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// c) Swap
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// I) RV32A
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'amoswap.w',
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// II) RV64A and RV128A
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'amoswap.d',
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'amoswap.q',
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// d) Add
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// I) RV32A
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'amoadd.w',
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// II) RV64A and RV128A
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'amoadd.d',
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'amoadd.q',
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// e) Logical
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// I) RV32A
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'amoxor.w',
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'amoand.w',
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'amoor.w',
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// II) RV64A and RV128A
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'amoxor.d',
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'amoand.d',
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'amoor.d',
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'amoxor.q',
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'amoand.q',
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'amoor.q',
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// f) Min\Max
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// I) RV32A
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'amomin.w',
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'amomax.w',
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'amominu.w',
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'amomax.w',
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// II) RV64A and RV128A
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'amomin.d',
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'amomax.d',
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'amominu.d',
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'amomax.d',
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'amomin.q',
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'amomax.q',
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'amominu.q',
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'amomax.q',
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// Part 7) Optional Floating-Point Instruction Extension: RVF, RVD, & RVQ
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// a) Move
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// I) RV32-
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'fmv.h.x',
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'fmv.s.s',
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'fmv.x.h',
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'fmv.x.s',
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// II) RV64- and RV128-
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'fmv.d.x',
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'fmv.q.s',
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'fmv.d.h',
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'fmv.q.s',
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// b) Convert
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// I) RV32-
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'fcvt.h.w',
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'fcvt.s.w',
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'fcvt.d.w',
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'fcvt.q.w',
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'fcvt.h.wu',
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'fcvt.s.wu',
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'fcvt.d.wu',
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'fcvt.q.wu',
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'fcvt.w.h',
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'fcvt.w.s',
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'fcvt.w.d',
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'fcvt.w.q',
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'fcvt.wu.h',
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'fcvt.w.s',
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'fcvt.w.d',
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'fcvt.w.q',
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// II) RV64- and RV128-
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'fcvt.h.l',
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'fcvt.h.t',
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'fcvt.h.lu',
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'fcvt.h.tu',
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'fcvt.s.l',
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'fcvt.s.t',
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'fcvt.s.lu',
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'fcvt.s.tu',
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'fcvt.d.l',
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'fcvt.d.t',
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'fcvt.d.lu',
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'fcvt.d.tu',
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'fcvt.q.l',
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'fcvt.q.t',
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'fcvt.q.lu',
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'fcvt.q.tu',
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'fcvt.l.h',
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'fcvt.t.h',
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'fcvt.lu.h',
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'fcvt.tu.h',
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'fcvt.l.s',
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'fcvt.t.s',
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'fcvt.lu.s',
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'fcvt.tu.s',
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'fcvt.l.d',
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'fcvt.t.d',
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'fcvt.lu.d',
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'fcvt.tu.d',
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'fcvt.l.q',
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'fcvt.t.q',
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'fcvt.lu.q',
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'fcvt.tu.q',
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// c) Load
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'flw',
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'fld',
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'flq',
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// d) Store
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'fsw',
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'fsd',
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'fsq',
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// e) Arithmetic
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'fadd.s',
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'fsub.s',
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'fmul.s',
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'fdiv.s',
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'fsqrt.s',
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'fadd.d',
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'fsub.d',
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'fmul.d',
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'fdiv.d',
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'fsqrt.d',
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'fadd.q',
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'fsub.q',
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'fmul.q',
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'fdiv.q',
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'fsqrt.q',
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// f) Mul-Add
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'fmadd.d',
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'fmsub.d',
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'fnmsub.d',
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'fnmadd.d',
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'fmadd.d',
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'fmsub.d',
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'fnmsub.d',
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'fnmadd.d',
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'fmadd.q',
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'fmsub.q',
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'fnmsub.q',
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'fnmadd.q',
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// g) Sign Inject
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'fsgnj.s',
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'fsgnjn.s',
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'fsgnjx.s',
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'fsgnj.d',
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'fsgnjn.d',
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'fsgnjx.d',
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'fsgnj.q',
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'fsgnjn.q',
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'fsgnjx.q',
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// h) Min/Max
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'fmin.s',
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'fmax.s',
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'fmin.d',
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'fmax.d',
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'fmin.q',
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'fmax.q',
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// i) Compare
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'feq.s',
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'flt.s',
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'fle.s',
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'feq.d',
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'flt.d',
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'fle.d',
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'feq.q',
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'flt.q',
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'fle.q',
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// j) Categorization
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'fclass.s',
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'fclass.d',
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'fclass.q',
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// k) Configuration
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'frcsr',
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'frrm',
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'frflags',
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'fscsr',
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'fsrm',
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'fsflags',
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'fsrmi',
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'fsflagsi',
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],
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'i'
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)
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// Registers
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// Part 1) Actual Register Values
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// Part 2) Application Binary Interface
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var registers = regexFromWords(
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[
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// Part 1) Actual Register Values
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'x0',
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'x1',
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'x2',
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'x3',
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'x4',
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'x5',
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'x6',
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'x7',
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'x8',
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'x9',
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'x10',
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'x11',
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'x12',
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'x13',
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'x14',
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'x15',
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'x16',
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'x17',
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'x18',
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'x19',
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'x20',
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'x21',
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'x22',
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'x23',
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'x24',
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'x25',
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'x26',
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'x27',
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'x28',
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'x29',
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'x30',
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'x31',
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// Part 2) Application Binary Interface
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'zero',
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'ra',
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'sp',
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'gp',
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'tp',
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't0',
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't1',
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't2',
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's0',
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's1',
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'a0',
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'a1',
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'a2',
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'a3',
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'a4',
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'a5',
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'a6',
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'a7',
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's2',
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's3',
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's4',
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's5',
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's6',
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's7',
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's8',
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's9',
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's10',
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's11',
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't3',
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't4',
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't5',
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't6',
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'pc',
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],
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''
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)
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// Keywords
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// Part 1) Pseudo Operations
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var keywords = regexFromWords(
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[
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// Part 1) Pseudo Operations
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'.align',
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'.file',
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'.globl',
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'.local',
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'.comm',
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'.common',
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'.ident',
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'.section',
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'.size',
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'.text',
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'.data',
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'.rodata',
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'.bss',
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'.string',
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'.asciz',
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'.asciiz',
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'.equ',
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'.macro',
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'.endm',
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'.type',
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'.option',
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'.byte',
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'.2byte',
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'.half',
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'.short',
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'.4byte',
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'.word',
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'.long',
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'.8byte',
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'.dword',
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'.quad',
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'.dtprelword',
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'.dtpreldword',
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'.sleb128',
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'.uleb128',
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'.p2align',
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'.balign',
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'.zero',
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'.float',
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'.double',
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],
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'i'
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)
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function normal(stream, state) {
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var ch = stream.next()
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|
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if (ch == '#') {
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stream.skipToEnd()
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return 'comment'
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}
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|
|
if (ch == '"' || ch == "'") {
|
|
state.cur = string(ch)
|
|
|
|
return state.cur(stream, state)
|
|
}
|
|
|
|
if (/\d/.test(ch)) {
|
|
stream.eatWhile(/[\w.%]/)
|
|
|
|
// Handle numeric labels
|
|
if (stream.peek() === ':') {
|
|
return 'variable'
|
|
}
|
|
|
|
return 'number'
|
|
}
|
|
|
|
if (/[.\w_]/.test(ch)) {
|
|
stream.eatWhile(/[\w\\\-_.]/)
|
|
|
|
return 'variable'
|
|
}
|
|
|
|
return null
|
|
}
|
|
|
|
function string(quote) {
|
|
return function (stream, state) {
|
|
var escaped = false,
|
|
ch
|
|
|
|
while ((ch = stream.next()) != null) {
|
|
if (ch == quote && !escaped) break
|
|
|
|
escaped = !escaped && ch == '\\'
|
|
}
|
|
if (!escaped) state.cur = normal
|
|
|
|
return 'string'
|
|
}
|
|
}
|
|
|
|
return {
|
|
startState: function (basecol) {
|
|
return { basecol: basecol || 0, indentDepth: 0, cur: normal }
|
|
},
|
|
|
|
token: function (stream, state) {
|
|
if (stream.eatSpace()) return null
|
|
|
|
var style = state.cur(stream, state)
|
|
|
|
var word = stream.current()
|
|
|
|
if (style == 'variable') {
|
|
if (keywords.test(word)) style = 'keyword'
|
|
else if (instructions.test(word)) style = 'builtin'
|
|
else if (registers.test(word)) style = 'variable-2'
|
|
}
|
|
return style
|
|
},
|
|
}
|
|
})
|
|
|
|
CodeMirror.defineMIME('text/riscv', 'riscv')
|